Kevin Townsend

Computing and Other Things

Hi, I am Kevin Townsend and unless I have been slow to update this page, I am a grad student at Iowa State University and a member of the Reconfigurable Computing Lab.

It can be tricky to explain what I do. I design processors. However, these processors will likely never be manufactured. Instead, I load this processor design onto an FPGA chip. Companies that make chip design tools call FPGA users the cheap seats, because loading a chip design on an FPGA is cheaper than manufacturing a chip. (Meaning they wont spend as much money on design tools.)

Two examples of processor designs I have created include a DNA aligner and a sparse matrix vector multiplier (SpMV).

Feel free to email me. I am also present on a few different sites: twitter, github, LinkedIn, Google Scholar, and chess.com, last.fm.

Publications

2014

  • O. Attia, T. Johnson, K. Townsend, P. Jones and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014.

2013

  • T. Zeng, K. Townsend, J. Duan, D.Chen. "A 15-bit binary-weighted current-steering DAC with ordered element matching", Proceedings of the Custom Integrated Circuits Conference (CICC), Sep. 2013.
  • K. Townsend and J. Zambreno, "Reduce, Reuse, Recycle (R3): A design methodology for sparse matrix vector multiplication on reconfigurable platforms", Application-Specific Systems, Architectures and Processors (ASAP), Jun. 2013.

2012

  • C. Nelson, K. Townsend, B. Rao, P. Jones and J. Zambreno, "Shepard: A fast exact match short read aligner", Formal Methods and Models for Codesign (MEMOCODE), Jul. 2012.